1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and, more particularly, to a semiconductor device having a recessed gate and asymmetric dopant regions and a method of manufacturing the same.
2. Description of the Related Art
Recently, integration of semiconductor devices has rapidly increased, and therefore, the channel length of transistors constituting each of the semiconductor devices has been sharply reduced. The short channel effect due to the decrease of the channel length causes several problems, by which the operational characteristics of the semiconductor device are deteriorated. For example, the strength of the electric field in the vicinity of the drain region is increased as the channel length is reduced. A hot carrier effect is generated by the increased strength of the electric field, and as a result, the operational characteristics and the stability of the semiconductor device are deteriorated. For a semiconductor memory device, such as a dynamic random access memory (DRAM), on the other hand, leakage current is generated as the strength of the electric field at the cell regions is increased, and the leakage current deteriorates the refresh characteristics of the semiconductor device.
In order to control the short channel effect, there have been recently proposed technologies to increase the effect channel length without reducing integration of the semiconductor device. For example, a recess cell structure and a step-gate asymmetric recess structure have been proposed. For the recess cell structure, a trench is formed at a substrate, and then the trench is filled with a gate conduction layer to form a gate stack. In the recess cell structure, the channel is formed around the trench, and therefore, the effective channel length is increased. For the step-gate asymmetric recess structure, on the other hand, a stepped profile is formed at the substrate, and a gate stack is formed at the stepped profile such that opposite side parts of the gate stack are disposed in an asymmetric fashion. In the step-gate asymmetric recess structure, the channel is formed along the stepped profile, and therefore, the effective channel length is increased.
In the recess cell structure and the step-gate asymmetric recess structure, the effective channel length is increased while the integration is not reduced, and therefore, the short channel effect is controlled. However, the amount of drain current is reduced due to the increase of the effective channel length with the result that the operational speed of the semiconductor device is reduced. This phenomenon is detrimental to semiconductor devices, such as graphic DRAM's, which are operated at high speed.